1. Field of the Invention
The present invention relates generally to the field of buried transistor circuits. More particularly, the present invention relates to an array of buried transistor cells including diffusion bit lines that are provided with a contact array structure for reducing resistance along the diffusion bit lines. Specifically, a preferred implementation of the present invention relates to floating gate (e.g., FLASH EPROM) memories that include a contact array structure that parallels one, or more, diffusion bit lines.
2. Discussion of the Related Art
It has been known in the field of microelectronics to connect buried transistors with diffusion bit lines. Prior art diffusion bit lines, sometimes called bit lines, are well known to those skilled in the art. U.S. Pat. Nos. 4,597,060; 5,399,891; 5,453,391; and 5,526,307, disclose floating gate memory circuits composed of buried transistor cells connected together with diffusion bit lines.
For instance, referring to FIG. 2, a conventional floating gate memory buried transistor subarray structure 200 is shown where the transistor cells are connected together with source diffusion areas and drain diffusion areas. The diffusion areas function as diffusion bit lines.
Still referring to FIG. 2, the conventional floating gate memory buried transistor subarray structure 200 includes a plurality of word lines 210. The plurality of word lines 210 function as the gates of the transistor cells that compose the conventional floating gate memory buried transistor subarray structure 200. Each of the plurality of word lines 210 passes over two channel areas 230. Between each of the plurality of word lines 210 and each of the two channel areas 230 is a floating gate (not shown). Thus, each of the plurality of word lines 210 is connected to two floating gates, and, therefore, two transistor cells. A source diffusion area 240 is located between the two channel areas 230. The source diffusion area 240 functions as the source for the transistors that compose the conventional floating gate memory buried transistor subarray structure 200. A pair of drain diffusion areas 250 are located next to the two channel areas 230. The pair of drain diffusion areas 250 are opposite the source diffusion area 240 with regard to the two channel areas 230. The pair of drain diffusion area 250 functions as the drain of the transistors that compose the conventional floating gate memory buried transistor subarray structure 200. A pair of isolation structures 260 are located adjacent to the pair of drain diffusion areas 250. Thus, the conventional floating gate memory buried transistor subarray structure 200 is depicted as having one subarray structure that includes two columns of transistor cells. The transistor cells in both columns share a common source diffusion bit line (i.e., the source diffusion area 240).
As represented in FIG. 2, each of the two channel areas 230 includes a plurality of dots. Each series of dots indicates that the conventional floating gate memory buried transistor subarray structure 200 can be expanded to include additional word lines. In addition, the conventional floating gate memory buried transistor subarray structure 200 can be expanded by extending the plurality of word lines 210 to the right and/or left to so that the conventional floating gate memory buried transistor subarray structure 200 would include additional column pairs.
Referring now to FIG. 3, a cross-section of the structure illustrated in FIG. 2, taken along the section line labeled B-Bxe2x80x2 in FIG. 2, is depicted. In FIG. 3, one of the plurality of word lines 210 runs continuously from one end of the structure to the other. The one of the plurality of word lines 210 is isolated from a pair of polywings 220 by an inter-poly dielectric 310. A pair of floating gates 330 are located beneath the pair of polywings 220 and are made of a first type of polycrystalline silicon (i.e., poly 1). The one of the plurality of word lines 210 is made of a second polycrystalline silicon (i.e. poly 2). The pair of polywings 220 are also made of polycrystalline silicon. The source diffusion area 240 and the pair of drain diffusion areas 250 are located beneath a buried diffusion BD oxide 320. The BD oxide 320 includes the pair of isolation structures 260. The two channel areas 230 are located below the pair of floating gates 330.
Referring now to FIG. 4 a cross-section of the structure illustrated in FIG. 2, taken along the section line labeled C-Cxe2x80x2 in FIG. 2, is depicted. In FIG. 4, each of the plurality of word lines 210 is separated by a spacer oxide 410. The plurality of word lines 210 and the spacer oxide 410 are formed on the BD oxide 320. The pair of drain diffusion areas 250 are located beneath the BD oxide 320.
As represented in FIG. 4, there are a series of dots to the right and left of the plurality of word lines 210. Each series of dots indicates that the conventional floating gate memory buried transistor subarray structure 200 can be expanded to include additional word lines. In addition, the conventional floating gate memory buried transistor subarray structure 200 can be expanded by adding additional word lines to the right and/or left. A global bit line 420 is located above, and spaced apart from the plurality of word lines 210.
A previously recognized problem with this diffusion bit line technology has been there can be significant voltage drops along such bit lines. Specifically, the voltage drop is severe for high current applications such as, for example, writing with hot electron programming on EPROM or FLASH EPROM circuits. Therefore, what is required is solution that reduces the electronic resistance of such diffusion bit lines.
Another previously recognized problem with this diffusion bit line technology has been that the read current and the read speed of circuits with longer buried diffusion lines are too low. Therefore, what is also required is a solution that enhances the read current and read speed with longer buried diffusion lines.
Another previously recognized problem with this diffusion bit line technology has been that the voltage/time (VT) distribution when writing to transistors connected with such buried diffusion lines by means of hot electron programming is unsatisfactorily wide. This is due to the large number of transistors that can be connected in parallel to such diffusion bit lines. Therefore, what is also required is a solution that tightens the voltage/time (VT) distribution when writing with hot electron programming.
Heretofore, the above-discussed requirements of reduced resistance, improved read current and speed, and tightened VT distribution have not been fully met. What is needed is a solution that simultaneously addresses these requirements.
A primary object of the invention is to provide reduced resistance along diffusion bit lines that interconnect buried transistors. Another primary object of the invention is to provide improved read current and speed for buried transistor arrays. Another primary object of the invention is to provide a tightened VT distribution when hot electron programming buried transistor memory circuits.
Therefore, there is a particular need to provide circuits that contain a buried transistor array with a contact array structure. Thus, it is rendered possible to simultaneously satisfy the above-discussed requirements of reduced resistance, improved read current and speed, and tightened VT distribution, which in the case of the prior art cannot be simultaneously satisfied.
A first aspect of the invention is implemented in an embodiment based on a method of operating a plurality of transistor cells with a contact array structure, comprising: applying a first voltage to a nonglobal conductor that is electrically coupled to a first plurality of transistor cells via a first plurality of contacts and a first diffusion bit line, wherein said first plurality of contacts is coupled to said nonglobal conductor, said first diffusion bit line is coupled to said first plurality of contacts, and said first plurality of transistor cells is coupled to said first diffusion bit line. A second aspect of the invention is implemented in an embodiment based on a floating gate memory, comprising a plurality of blocks of transistor cells, each of said plurality of blocks including a plurality of subarrays of transistor cells, each of said plurality of subarrays of transistor cells including: a first plurality of buried transistor cells; a first drain diffusion bit line coupled to said first plurality of buried transistor cells; a first plurality of contacts coupled to said first drain diffusion bit line; a first nonglobal conductor coupled to said first plurality of contacts; a source diffusion bit line coupled to said first plurality of transistors; a second plurality of contacts coupled to said source diffusion bit line; a second nonglobal conductor coupled to said second plurality of contacts; a second plurality of buried transistor cells coupled to said source diffusion bit line; a second drain diffusion bit line coupled to said second plurality of buried transistor cells; a third plurality of contacts coupled to said second drain diffusion bit line; and a third nonglobal conductor coupled to said third plurality of contacts. A third aspect of the invention is implemented in an embodiment based on a contact array structure for a plurality of transistors, comprising: a first diffusion bit line coupled to said plurality of buried transistors; a first plurality of contacts coupled to said first diffusion bit line; and a first nonglobal conductor coupled to said first plurality of contacts.
These, and other, objects and aspects of the present invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating preferred embodiments of the present invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the present invention without departing from the spirit thereof, and the invention includes all such modifications.